1. Technical Field
The present application relates to an apparatus, method and program for controlling a communication bus which is implemented as a network on a semiconductor chip.
2. Description of the Related Art
Recently, as the functionalities of SoC (system on chip) and processors have been further enhanced, NoC (network on chip) that is a network type bus has attracted more and more attention and has been replacing ordinary communication buses. In an NoC, a lot of bus masters and memories can be connected together.
FIGS. 1A and 1B illustrate a configuration for a part of an NoC bus. Specifically, FIG. 1A illustrates an exemplary hardware connection and FIG. 1B is a schematic representation thereof. As shown in FIGS. 1A and 1B, bus masters 1a, 1b and 1c, all of which are integrated together on a single chip 10, are connected to the same bus 3 by way of their associated bus masters (R) 2. It should be noted that in the drawings of this application, an NoC bus is represented as in the schematic representation shown in FIG. 1B.
FIG. 2 illustrates an exemplary configuration for an NoC bus in which a number of bus masters are coupled together to form a two-dimensional mesh. In this example, a router node R for performing a control on a data transfer route is provided for each of various bus masters including microprocessors, DSPs, memories and input/output circuits. And two adjacent ones of those router nodes R are connected (i.e., linked) together with a short line. In this description, the router node R will also be referred to herein as sometimes a “router” and sometimes a “bus controller”.
In such a configuration, data can be transferred from a bus master on the transmitting end (i.e., source) to a bus master on the receiving end (i.e., destination) through a number of different communication routes. For example, FIG. 3 illustrates three routes (1), (2) and (3) leading from the source to the destination.
By choosing the best one of multiple candidate routes according to the load imposed on the bus, the data to transfer can be efficiently distributed over the entire chip and an increase in average bus use efficiency can be expected. That is why the throughput of the overall bus increases, the operating frequency of the bus can be reduced during a design process or during the operation, and the power dissipated by the chip can be cut down. In addition, since the data transfer latency (time delay) between bus masters can be reduced, the performance of the bus masters can be made full use of, which eventually leads to improving the overall processing performance of the chip.
Japanese Patent No. 3816531 discloses a method for choosing one of multiple data transfer routes according to the status of a bus that connects multiple bus masters together. According to the technique disclosed in Japanese Patent No. 3816531, data is transferred on a frame-by-frame basis from a bus master on the transmitting end to a bus master on the receiving end. If the frame transmitted has been received successfully at the receiving end, acknowledge data is returned. Otherwise, no acknowledge data is returned. Thus, if no acknowledge data is returned, the bus master on the transmitting end senses that the transfer of that frame has failed. In that case, the bus master changes the transfer routes into another one and re-transmits that frame through it. In this manner, communications can be continued. If any error has been detected in the header of the frame received, then the bus master on the receiving end discards that frame, and therefore, the bus master on the transmitting end never receives any acknowledge data in that case. Likewise, if the frame transfer latency on the data transfer route currently chosen is too long for the frame to arrive at the receiving end within a predetermined period of time, the bus master on the transmitting end cannot receive the acknowledge data within the predetermined time. Then, the routes also need to be changed. By changing the data transfer routes dynamically in this manner according to the status of the route currently used, communications can be made through a route with less transfer latency or error.